1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, a semiconductor device including a logic semiconductor integrated circuit such as a CMOS logic LSI and a method of producing the semiconductor device.
Improvement in circuit performance and increase in integration density of a semiconductor integrated circuit (LSI) have been achieved by making a circuit pattern finer. In particular, in a logic LSI, its operating speed (operating frequency) has been improved by shortening a transistor gate length (Lg).
In formation of the circuits, photolithography (reduction projection exposure method) is used at present. The resolution has been improved by shortening the exposure wavelength and increasing numerical aperture of projection optics.
At present, the transistor gate length Lg has been shortened to 0.18 micron by using a KrF excimer laser exposure apparatus (wavelength of 248 nm). The intervals (pitches) of gates and wires have been being reduced to improve the integration density. It is presumed that 0.5 micron or less can be realized by using the KrF exposure apparatus.
It is expected that by using an ArF excimer laser exposure apparatus (wavelength of 193 nm), each of the transistor gate length Lg and the pitch can be reduced further by about 20 percent, but it is difficult to realize further reduction by a conventional reduction projection exposure method using deep ultra-violet radiation.
On the other hand, in photolithography, as a method of improving resolution without changing optics, a phase shifting mask is known. According to the method, by controlling (usually, inverting) the phase of light passing through a specific aperture in the mask, the resolution of the optics is improved much more than the case of using a conventional mask.
Among various kinds of phase shifting masks, an alternating phase shifting mask produces the highest effect on improvement in resolution.
The phase shifting method is described in, for example, xe2x80x9cULSI Lithography Technical Renovationxe2x80x9d, SCIENCE FORUM TOKYO, pp. 34-40, 1994.
Although the alternating phase shifting method is easily applied to alternating patterns as the name implies, generally, it cannot be always applied to a pattern of an arbitrary shape. For example, it is difficult to dispose a shifter in the case of a U-letter shaped pattern or three aperture patterns arranged at the shortest distance.
A method of performing multiple-exposure onto the same resist film by using a plurality of masks including the phase shifting mask to enable an arbitrary-shaped pattern to be transferred has been applied by the inventors of the present invention in Japanese Patent Nos. 2650962 (Publication of Japanese Unexamined Patent Application No. 1-283925) and 2638561 (Publication of Japanese Unexamined Patent Application No. 8-51068). The method is applied to, for example, a process of forming a gate of a logic LSI which has to be formed by controlling the line width of an extremely thin line pattern with high accuracy. Specifically, by disposing a phase shifter (region in which the phase of transmission light is inverted on a mask) so that the phases in the apertures on both sides of a gate are inverted, the resolution, line width accuracy, depth of focus, and the like of a transistor gate pattern can be largely improved.
Since an edge portion of the phase shifter is, however, generally transferred as an unnecessary pattern, in order to prevent it, it is necessary to divide an original design pattern into two mask patterns and perform multiple exposure.
For example, multiple exposure is performed on the same positive resist film by using two masks of a first mask 1A as shown in FIGS. 1A-1B and a second mask 1B as shown in FIG. 1C and developed. The first mask 1A has apertures 1a and 1b on both sides of a part (indicated as a region a) corresponding to a fine gate in an active region. A phase shifter 2 is provided for one of the apertures, for example 1a, so that the phases of light passing the apertures 1a and 1b neighboring the region (a) corresponding to the gate are opposite to each other. The second mask 1B includes a light shielding pattern 3 for covering the gate (region a) and a light shielding pattern 4 formed in the same layer as the light shielding pattern 3, for covering the region other than the fine gate.
Consequently, as shown in FIG. 1D, a desired resist pattern 5 is formed on a wafer. Narrow portions of the resist pattern 5 correspond to the gate mask formed by the light shielding pattern 3 of the second mask 1B. Similarly, thick portions correspond to the mask which is, for example, a wiring pattern formed by the light shielding pattern 4 of the second mask 1B.
The patterns on the two masks can be automatically generated from the original design pattern by a geometrical operation and a dedicated program for automatically generating patterns has been also developed.
It is considered that by using the method, the transistor gate length Lg can be reduced to about 0.12 micron by employing a KrF exposure apparatus. The combination of the masks to form the resist pattern of FIG. 1D is not limited to that of the masks 1A and 1B. For example, in place of the mask 1B, a mask 1D in which light shielding portions on fine gates are broadened as shown in FIG. 1E can be used.
The improvement in accuracy of the dimension is as important as the reduction in the transistor gate length Lg. The required dimensional accuracy of the a transistor gate length Lg is about 10% of normal design dimension. When the KrF exposure apparatus is used, it is therefore necessary to perform a dimension control at a 10 nm level. One of factors of deterioration in dimensional accuracy is a proximity effect such that the dimension and shape of a pattern fluctuate due to an influence of adjacent patterns.
Specifically, when transistor gate patterns (narrow portions) having uniform length Lg variously disposed as design mask patterns as shown in (a) of FIG. 2A are transferred onto a wafer, as shown in (b), the dimensions of actually etched gate patterns change according to the disposing state of the designed patterns. That is, as shown in the diagram, the designed gate pattern (narrow portion) becomes thick as a whole or partially.
It is known that the phenomenon is caused by complicatedly connected various effects such as a pure optical effect by diffraction of light, diffusion of reaction products in the resist, dependence on a developed area of a development rate, and a (micro)loading effect at the time of etching.
In order to solve the problem, therefore, an optical proximity effect correction technique for correcting the dimension of a mask pattern in consideration of the proximity effect has been being examined. To be specific, as schematically showing a correction mask in (c) of FIG. 2B, by correcting the design dimension of the transistor gate length Lg on the mask, the dimension of the gate pattern actually obtained on a wafer can be uniformized as shown by (d) in FIG. 2.
The correction of the light proximity effect is described in, for example, Proceedings of SPIE, Vol. 3334, pp. 921-931, 1998.
The proximity effect correction has, however, a problem such that very long time is required for a correction since a pattern is designed by estimating the degree of the proximity effect. Particularly, in the case of using a phase edge, a problem such that a correction rule is complicated. Further, exposure characteristics largely vary according to a distance to an adjacent gate. Especially, since the manner of a change in line width in association with deforcusing (hereinbelow, called defocus characteristics) largely varies, the following problem arises. Even if the proximity effect is corrected under certain optimum focusing conditions, when defocusing occurs on an actual wafer, the effect of the correction is lost.
Focus characteristics for the same design dimension patterns disposed at different pitches draw, for example, two curves shown in FIG. 3A (before the proximity effect correction). When a proximity effect is corrected so as to equalize the dimensions of the two patterns at the optimum focal point position (defocus=0), the focus characteristics of the patterns become as shown in FIG. 3B. It is understood that line width variations in a presumed range of focal variation are not improved.
The proximity effect becomes more conspicuous as the distance between the patterns is shortened. Particularly, the problem including the change in defocus characteristics becomes more conspicuous when the distance between the centers of the patterns equal to or is smaller than 2 xcex/NA (xcex denotes exposure wavelength and NA denotes numerical aperture of an exposure apparatus). When the phase shifting method is used, the pitch of gates can be reduced, so the problem becomes more serious.
Further, in the phase shifting method, the degree of spatial coherence of an exposure apparatus is often set to be high (the coherence factor "sgr" is set to be small). In this case, the proximity effect is more conspicuous. The proximity effect largely varies according to conditions of a process of forming a resist film and etching after exposure. On the other hand, once a mask is produced, it is difficult to correct or change it. Consequently, the proximity effect correction method also has a problem that it does not easily cope with a change or variation in process conditions.
It is therefore a first object of the invention to solve the problems of the conventional phase shifting method and to provide a high-performance semiconductor device in which variation in gate length caused by the proximity effect is suppressed. Further, it is a second object to provide a method of producing a semiconductor device capable of reducing the gate length and the pitch of gates while suppressing variation in gate length caused by the proximity effect when a semiconductor device in which the gate length is 0.2 micron or less is formed by photolithography.
The first object is achieved by a semiconductor device in which a dummy gate pattern which has the same device structure as that of a gate but is electrically inactive (that is, having no circuit function) is provided adjacent with a predetermined distance to a transistor gate pattern which is requested to be very accurate, formed in an active region, and is electrically active (that is, having a circuit function), wherein the minimum distance between the transistor gate pattern in the active region and another transistor gate pattern in the active region or the dummy gate pattern adjacent to the gate pattern in the active region is made substantially constant.
Preferably, when a distance P between the centers of the neighboring gate patterns or between the center of the transistor gate pattern and the center of the dummy gate pattern is 2xcex/NA or shorter (where, xcex denotes an exposure wavelength and NA denotes a numerical aperture of an exposure apparatus), an amplitude of variation in the distance is suppressed within xc2x110%.
Further, the transistor gate pattern is achieved by being formed in a portion corresponding to an edge of a phase shifter in a phase shifting mask. The phase shifter has a constant line width within a range of the amplitude of variation when the width is converted to the distance on a wafer.
The transistor gate patterns may be also designed so as to be arranged on one-dimensional lattices arranged at predetermined intervals within a predetermined region. The dummy gate pattern may be removed after forming the transistor gate pattern (after etching) as necessary.
The second object is achieved by a method of producing a semiconductor device, comprising a step of performing exposure by using an alternating phase shifting mask in which a shifter line width L in the direction of transistor gate length is substantially constant, thereby forming a designed desired transistor gate pattern in a part of a shifter edge of the phase shifting mask and forming a dummy gate pattern having the same device structure as that of the gate but having no circuit function in the remaining portion of the shifter edge so as to be isolated from the transistor gate pattern, wherein each of a distance between the centers of the neighboring transistor gate patterns and a distance between the center of the transistor gate pattern and the center of the dummy gate pattern is 2xcex/NA or smaller (where, xcex denotes an exposure wavelength and NA denotes a numerical aperture of an exposure apparatus) and its amplitude of variation is suppressed within xc2x110%, thereby making the minimum distance between each of all the transistor gate patterns and each of all the dummy gate patterns substantially constant.
When exposure is performed by using the phase shifting mask in practice, it is desirable to consider a reduction ratio of optics of a reduction projection exposure apparatus used. In this case, it is preferable to set the shifter line width L of the phase shifting mask to 2xcex/(NAxc3x97M) or smaller (where, M denotes a reduction ratio of optics used for exposure) and to set the amplitude of variation in shifter line width L within xc2x110%.
Further, the object is achieved by a method of producing a semiconductor device comprising: a step of designing a transistor gate pattern in a predetermined region where transistor gates exist in a semiconductor device so as to be disposed on a predetermined one-dimensional lattice, and performing multiple-exposure on the same resist formed on a semiconductor substrate by using: a first alternating phase shifting mask including a phase shifter which has a width substantially equal to a pitch of the lattice in the region within the amplitude of variation and is disposed so that an edge of the phase shifter substantially coincides with a center line of a desired transistor gate pattern; and a second mask in which a region including at least the transistor gate pattern is used as a light shielding region; a step of developing the resist film to thereby form resist patterns; and a step of etching a film to be processed on the semiconductor substrate by using the resist patterns as a mask. Preferably, at least portions on the lattice on both sides (in the direction of transistor gate length Lg) of the transistor gate pattern are included in the light shielding region of the second mask.
As shown in FIG. 1A which has been used to describe the principle of the conventional phase shifting method, in the first phase shifting mask 1A, two apertures 1a and 1b exist on both sides of the light shielding area (a) as a gate mask pattern. When the phase of light transmitting one of the apertures, for example 1a, is almost inverted by the phase shifter 2, as shown in partial magnification of FIG. 1B, a point which is in almost the center of the light shielding area (a) and is located equidistant from both edges of the two apertures 1a and 1b (that is, the position which is in the middle of the width of the light shielding area (a)) is defined as a phase edge 6 (shown by the broken line in the partial magnification).
Therefore, it does not always coincide with the edge of the outline of a phase shifter pattern on mask data for forming the phase shifting mask 1A or the edge of a mask substrate digging region for shifting a phase on an actual mask.
The distance from the phase edge defined as above and a neighboring phase edge over a region of a phase of 0 degree or a region of a phase of 180 degrees is defined as shifter line width L.